By KiddieDaily Editors · 2026-06-29 · 2 min read · 1 source

IBM creates world's first sub-1nm computer chip — cramming 100 billion transistors into a tiny fingernail-sized space

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The new 0.7 nm transistors are significantly smaller than those that feature in standard 2 nm semiconductor chips used in supercomputers, AI systems and advanced graphics processing units (GPUs). While size designation doesn't necessarily correlate with an exact measurement of the transistors on the chips, it does represent their general capabilities. Essentially, the smaller the transistors and their supporting components, the more you can fit on a chip.

A typical 2 nm chip design, for example, can fit roughly 50 billion transistors onto a space the size of a human fingernail. The new chip features transistors that are so diminutive they're not measured in nanometers but "angstroms," a unit of measurement typically reserved for atoms. The first of these chips is expected to be manufactured with transistors that are a mere 7 angstroms — equivalent to 0.7 nanometers or roughly the width of a glucose molecule.

At this size, engineers can squeeze nearly 100 billion transistors into a fingernail-size space — nearly twice that of the current 2 nm platform. The scientists achieved this feat using a novel technique called "nanostacking," which they first outlined in a study published as part of the peer-reviewed 2025 Symposium on VLSI Technology and Circuits and uploaded July 2025 to the IEEE Xplore server. This enables engineers to vertically stack the nanosheets used to build the previous generation of 2 nm computer chips.

The technology used in all conventional circuits — known as complementary metal-oxide-semiconductor (CMOS) — demands extremely high temperatures during manufacturing. As transistors shrink, they also suffer from issues such as "charge trapping" — where electrons or holes become immobilized by defects or impurities — and "gate leakage" — static power dissipation. Get the world’s most fascinating discoveries delivered straight to your inbox.

Such problems have posed a challenge to attempts to shrink transistor size below 2 nm, and thus improve the performance and efficiency of computer chips beyond today's best capabilities. IBM's three-dimensional stacked architecture, however, aims to alleviate some of these pain points, the scientists said.

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